1. Field of the Invention
The present invention relates to a capacitive element, designing method of the same and integrated circuit device including the same, and more particularly to a capacitive element formed by multilayer wirings in an integrated circuit, designing method of the same and integrated circuit device including the same.
2. Description of the Related Art
Recent years have witnessed a remarkable progress in the semiconductor manufacturing techniques, mass-producing semiconductors with a minimum feature size of 0.1 μm or less. With the miniaturization of devices, process variations which were not problematic in the previous generation have led to unintended performance of the manufactured devices.
Of all circuit characteristics, the capacitance variation of the capacitive element affects the performance of analog devices the most significantly. Therefore, the capacitance variation of the analog elements is the most essential factor in terms of performance and therefore rigorously managed. Among examples of analog devices is a capacitance-type DA (digital to analog) converter.
A capacitance-type DA converter includes a plurality of capacitive elements connected in parallel. Such capacitive elements should preferably have a completely linear relationship between the number of capacitive elements and obtained characteristics (e.g., current and voltage levels) as illustrated in FIG. 15. Practically, however, there are variations between the capacitive elements, possibly resulting in unintended performance due to a non-linear relationship. Therefore, it is common to use capacitive elements with a large area in order to reduce element-to-element variations.
However, using elements with a large area leads to increased chip area as a whole and increased power consumption. That is, increase in chip area and achievement of intended performance (reduced capacitance variations) are in a tradeoff relationship. The graph in FIG. 16 is a Peligrom plot showing the area of the capacitive elements (1/(area)1/2) along the horizontal axis and the capacitance variations along the vertical axis.
When the variation threshold (dashed line parallel to the x axis) is fixed in this graph, the smaller the variation between the elements (solid line), the smaller the area. This makes it possible to reduce the chip area and power consumption. In order to intentionally suppress the variations between the elements, however, there has been hitherto no other alternative but to suppress the process variations by increasing, for example, the wiring width of the elements themselves knowing that doing so will result in increased area.
An existing technique known to solve these problems is a device structure having a one-to-one relationship between a width W of wirings forming the capacitive elements and a wiring-to-wiring spacing S (refer, for example, Japanese Patent No. 3851898 and U.S. Pat. No. 5,583,359, hereinafter referred to as Patent Documents 1 and 2). The device structure having a one-to-one relationship between the wiring width W and spacing S will be hereinafter referred to as the close-packed structure. The close-packed structure has been chosen because an element having this structure offers the smallest area.